Synopsys Design Compiler Tutorial | 2021 _top_

To use Synopsys Design Compiler, you need to:

dc.read_verilog(['rv32i_core.v', 'alu.v']) dc.current_design('rv32i_core') dc.create_clock('clk', period=1.0) dc.compile_ultra(timing_high_effort=True) dc.write_verilog('outputs/rv32i_core.v') synopsys design compiler tutorial 2021

Let’s walk through a practical session using a simple 32-bit RISC-V processor (e.g., rv32i_core.v ). We’ll target a library (simulated in the tutorial). To use Synopsys Design Compiler, you need to: dc