Xilinx Ise 10.1 |verified| Site

: Managed translation, mapping, placing, and routing (PAR) onto targeted silicon.

, a legacy design environment used for developing firmware for Xilinx FPGA and CPLD families . Though succeeded by xilinx ise 10.1

and supported synthesis for VHDL and Verilog 2001 (though it lacked full SystemVerilog support www.academia.edu Common Use Cases : Managed translation, mapping, placing, and routing (PAR)